The SpyGlass®-DFT solution has the unique ability to predict ATPG (automatic test pattern generation) test coverage and pinpoint testability issues as the RTL description is developed, even before a gate-level netlist is generated. The SpyGlass-DFT solution not only detects testability issues--it can also automatically correct them.

The benefits are substantial. Traditional approaches depend on test engineers to design test clocks and set/reset logic for scan insertion at the gate level, when changes can be difficult, time-consuming and expensive. The SpyGlass-DFT solution, by contrast, enables users to tune testability during RTL creation, when the design impact is greatest and the cost of modifications lowest. The SpyGlass-DFT solution can significantly shorten development cycles, reduce costs and improve overall testability.


Accurately Predicts Test Coverage at RTL; Extensible DFT Rules

The SpyGlass-DFT solution predicts test coverage at RTL (before synthesis and scan insertion) with extraordinary accuracy: often within 1 percentage point of the final ATPG number. It also helps ensure that the RTL is compliant with the requirements for scan insertion and ATPG.

The SpyGlass-DFT solution includes a comprehensive set of over 100 design-for-test rules. Users can also write their own rules to enforce company-specific DFT practices and policies. The solution features a unique AutoFix ability to automatically correct RTL code for improved scannability.

The SpyGlass-DFT solution includes an intuitive design and diagnostic environment combining RTL design capture and browsing with schematic visualization. Users can easily cross-probe between violation reports, schematics and RTL windows to trace problems to their source and make appropriate changes.

At-speed Testing Problem

The test clocks in traditional stuck-at testing are designed to run on the test equipment at frequencies lower than the system speed. At-speed testing requires test clocks to be generated at the system speed, and therefore are often shared with functional clocks from a phase locked loop (PLL) clock source. This additional test clocking circuitry affects functional clock skew, and thus the timing closure of the design. 

At-speed tests often result in lower than required fault coverage even with full-scan and high (>99%) stuck-at coverage. Identifying reasons for low at-speed coverage at ATPG stage is too late to make changes to the design and affects schedules significantly.

The Methodology

Atrenta's SpyGlass-DFT solution methodology provides easy-to-use and a comprehensive method for solving Design-for-Test problems at RTL to ensure higher test quality

• Provides methodology documentation and rule-sets as part of the product
• The user-guided DFT sub-methodology results in fewer but meaningful violations, thus saving time for the RTL designer
• Walks users through a series of recommended steps to analyze DFT violations at block and chip level - the steps include design setup, defining initial test signals, scan wrapping black boxes, using by-pass constraints for modules with internal by-pass logic, achieving scannability, making latches transparent, adding test points, and validating scan chains

• Pinpoints and diagnoses DFT issues at RTL or gate level
• Predicts ATPG test coverage with high correlation (within 1% of final ATPG result)
• Pinpoints causes that block high at-speed coverage
• Ensures that RTL is scan-compliant
• Built-in controllability and observability engine analyzes testability strategies
• Guides selection of highest-value test points
• Unique AutoFix capability automatically corrects RTL to improve scannability
• Intuitive, integrated debug environment with cross-probing among views

SpyGlass-DFT DSM
The product option introduces advanced timing closure analysis and RTL testability improvement for deep submicron (DSM) defects associated with at-speed testing.

Traditionally, designers synthesize the design first to a gate level representation and then hand it over to the ASIC vendor to insert MBIST logic at the netlist level.

When MBIST is inserted at the gate level:
• Functional verification takes longer and is expensive is not in control of the system house/designer
• Optimization during synthesis/early floor-planning does not take MBIST logic into account
• BIST sharing schemes and architectural trade-offs could result in many design iterations through RTL synthesis and floor planning
• RTL for the design does not remain golden for IP handoff/reuse

Designers need a RTL solution that is flexible and easily integrates with any vendor's BIST IPs and provides automation for BIST insertion at RTL.