The SpyGlass®-DFT solution has the unique ability to predict ATPG (automatic test pattern generation) test coverage and pinpoint testability issues as the RTL description is developed, even before a gate-level netlist is generated. The SpyGlass-DFT solution not only detects testability issues--it can also automatically correct them. The benefits are substantial. Traditional approaches depend on test engineers to design test clocks and set/reset logic for scan insertion at the gate level, when changes can be difficult, time-consuming and expensive. The SpyGlass-DFT solution, by contrast, enables users to tune testability during RTL creation, when the design impact is greatest and the cost of modifications lowest. The SpyGlass-DFT solution can significantly shorten development cycles, reduce costs and improve overall testability.
Accurately Predicts Test Coverage at RTL; Extensible DFT Rules
The SpyGlass-DFT solution predicts test coverage at RTL (before synthesis and scan insertion) with extraordinary accuracy: often within 1 percentage point of the final ATPG number. It also helps ensure that the RTL is compliant with the requirements for scan insertion and ATPG.
The SpyGlass-DFT solution includes a comprehensive set of over 100 design-for-test rules. Users can also write their own rules to enforce company-specific DFT practices and policies. The solution features a unique AutoFix ability to automatically correct RTL code for improved scannability.
The SpyGlass-DFT solution includes an intuitive design and diagnostic environment combining RTL design capture and browsing with schematic visualization. Users can easily cross-probe between violation reports, schematics and RTL windows to trace problems to their source and make appropriate changes.
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