SpyGlass® Advanced Lint

Deeper Design Analysis for RTL Designers

Using advanced formal analysis, SpyGlass Advanced Lint pinpoints deeper functional problems in RTL designs without requiring test benches or assertions. SpyGlass Advanced Lint ensures that design intent is correct by verifying control logic (FSM), synchronous FIFOs, signals toggling, bus integrity (contention, floating state, index overflow) and design initialization. The resulting RTL is more optimized and verifiable with comprehensive FSM style reporting and detection of logic redundancies (dead code). This improves the area, timing, power and testability of your design. SpyGlass Advanced Lint also provides a design complexity DashBoard for tracking RTL quality as it is developed. It complements the extensive structural linting checks of the base SpyGlass solution.

Preventing Chip-killer Bugs

Chip killer bugs can escape today's verification solutions, especially related to FSMs synchronous FIFOs. For example, unintended FSM behavior, dead code and incomplete initialization are areas that every designer wants to get right, but often fails because of changes very late in a design cycle. In addition, creating test vectors and assertions is getting too complex and time-consuming. Poor chip quality regarding area, power, testability and timing can result from these problems.

The Methodology

Atrenta's GuideWare Reference Methodology provides a structured, easy to use, and comprehensive method for solving RTL design issues, thereby ensuring high quality RTL with fewer design bugs.

  • Predefined flows, which can be customized, along with documentation, and rule sets, are provided
  • Provides ways to debug and resolve critical issues related to FSM's, dead code and initialization in the RTL development phase
  • Explains how the DashBoard can be used to track RTL design complexity as it is developed

Features & Benefits

  • Uses formal techniques to analyze RTL without requiring assertion or stimulus
  • Analyzes FSM's in the design: Identifies deadlocked and unreachable states, minimizes late stage design changes
  • Analyzes synchronous FIFOs in design to report underflow and overflow
  • Reports dead code in the design to determine if it is unintentional, preventing incorrect functionality
  • Analyzes initialization of flip-flops as uninitialized flops will lead to unknown states, preventing correct functionality
  • Reports signals toggling and bus integrity issues such as bus contention, floating state and index overflow
  • Provides a design complexity DashBoard for tracking RTL quality to manage the design progress
  • Provides full debug capabilities at RTL including cross-probing between RTL and violations, graphical FSM viewer, spreadsheets, schematics and a waveform viewer
  • Supports Verilog, VHDL, V2K, SystemVerilog and mixed-language designs