Deeper Design Analysis for RTL Designers
Using advanced formal analysis, SpyGlass Advanced Lint pinpoints deeper functional problems in RTL designs without requiring test benches or assertions. SpyGlass Advanced Lint ensures that design intent is correct by verifying control logic (FSM), synchronous FIFOs, signals toggling, bus integrity (contention, floating state, index overflow) and design initialization. The resulting RTL is more optimized and verifiable with comprehensive FSM style reporting and detection of logic redundancies (dead code). This improves the area, timing, power and testability of your design. SpyGlass Advanced Lint also provides a design complexity DashBoard for tracking RTL quality as it is developed. It complements the extensive structural linting checks of the base SpyGlass solution.
Preventing Chip-killer Bugs
Chip killer bugs can escape today's verification solutions, especially related to FSMs and synchronous FIFOs. For example, unintended FSM behavior, dead code and incomplete initialization are areas that every designer wants to get right, but often fails because of changes very late in a design cycle. In addition, creating test vectors and assertions is getting too complex and time-consuming. Poor chip quality regarding area, power, testability and timing can result from these problems.
Atrenta's GuideWare Reference Methodology provides a structured, easy to use, and comprehensive method for solving RTL design issues, thereby ensuring high quality RTL with fewer design bugs.
Features & Benefits