SpyGlass® CDC

Closing the Verification Gap

Signoff Quality CDC Solution for Billion+ Gate Designs
Atrenta Webinar

This webinar discusses how SpyGlass® CDC provides a scalable solution to deliver the highest throughput and signoff quality CDC verification closure for billion+ gate designs.

Watch this Webinar Replay

Among the many verification challenges confronting system-on-chip (SoC) designers today, clock domain crossings (CDC) ranks near the top in difficulty. Today's SoCs have dozens or sometimes even hundreds of asynchronous clock domains, which is very difficult to verify using conventional simulation or static timing analysis (STA). RTL simulation is not designed to verify issues exhibited by data transfer across asynchronous clock boundaries and STA does not address asynchronous clock domains issues. As a consequence, CDCs have become a leading cause of design errors. Such errors can add significant time and expense to the design-and-debug cycle, and may even find their way into silicon, necessitating costly re-spins.

Comprehensive, Practical, and Powerful CDC Analysis

Conventional static CDC analysis tools do too little and too much at the same time, simultaneously overlooking real design errors and over-reporting large numbers of false violations. As a result, users are forced into an endless bug-hunting process, which often leaves the real bugs undetected. The Protocol Independent Analysis technology that is part of SpyGlass CDC and addresses these issues in an easy to use fashion. SpyGlass CDC addresses structural and functional CDC problems. For structural analysis, users have the flexibility to use a flat CDC analysis or use a hierarchical SoC flow to support IP based design methodologies and achieve quickest turnaround time for very large SoCs. For functional CDC, users have the flexibility to use formal verification based or simulation based analysis.

The Methodology

Atrenta's SpyGlass GuideWare methodology provides a structured, easy to use and comprehensive method for solving RTL design issues, thereby ensuring high quality RTL with fewer design bugs.

  • Methodology documentation and rule-sets are provided as part of the product
  • The user-guided CDC methodology results in fewer but meaningful violations, thus saving time for the RTL designer
  • SpyGlass CDC walks users through a series of recommended steps to analyze CDC problems at the block level as well as the chip level - the steps include design setup, setup checks, design-unit integration and chip level CDC verification, report review and CDC verification signoff
CDC Pillar

Features & Benefits

  • Architecture based on 6 Pillars of Scalable CDC Verification
  • Simple setup by automatically extracting the clock, reset and clock domains information; It can also extract the same information from existing SDC constraints providing a jump start to the users
  • Comprehensive structural and functional CDC analysis using formal based and simulation based solutions to deliver signoff quality CDC verification
  • Protocol Independent Analysis, recognition of widest variety of synchronizers and auto detection of quasi-static signals resulting in the lowest number of false violations
  • Highest performance and CDC centric debug capabilities
  • Hierarchical SoC flow to support IP based design methodologies to deliver quickest turnaround time for very large size SoCs
  • Integrates with Atrenta SpyGlass platform which targets other RTL like analysis, like constraints, DFT, congestion, and power
  • Low learning curve and ease of adoption