Closing the Verification Gap
Among the many verification challenges confronting system-on-chip (SoC) designers today, clock domain crossings (CDC) ranks near the top in difficulty. Today's SoCs have dozens or sometimes even hundreds of asynchronous clock domains, which is very difficult to verify using conventional simulation or static timing analysis (STA). RTL simulation is not designed to verify issues exhibited by data transfer across asynchronous clock boundaries and STA does not address asynchronous clock domains issues. As a consequence, CDCs have become a leading cause of design errors. Such errors can add significant time and expense to the design-and-debug cycle, and may even find their way into silicon, necessitating costly re-spins.
Comprehensive, Practical, and Powerful CDC Analysis
Conventional static CDC analysis tools do too little and too much at the same time, simultaneously overlooking real design errors and over-reporting large numbers of false violations. As a result, users are forced into an endless bug-hunting process, which often leaves the real bugs undetected. The Protocol Independent Analysis technology that is part of SpyGlass CDC and addresses these issues in an easy to use fashion. SpyGlass CDC addresses structural and functional CDC problems. For structural analysis, users have the flexibility to use a flat CDC analysis or use a hierarchical SoC flow to support IP based design methodologies and achieve quickest turnaround time for very large SoCs. For functional CDC, users have the flexibility to use formal verification based or simulation based analysis.
Atrenta's SpyGlass GuideWare methodology provides a structured, easy to use and comprehensive method for solving RTL design issues, thereby ensuring high quality RTL with fewer design bugs.
Features & Benefits