SpyGlass® Constraints

Specify Constraints Early, Validate Continuously & Automate Handoff

Creating and ensuring correct and consistent constraints, at all levels of the design hierarchy and throughout the design cycle, is a vital and increasingly challenging task. The difficulties can include: writing new constraints, managing thousands of lines of legacy constraints, managing thousands of timing exceptions, experiencing unwanted iterations due to changing constraints and implementing erroneous constraints resulting in redesigns or even re-spins. 

The SpyGlass® Constraints solution provides a productivity boost to IC design efforts by automating the creation, validation and management of constraints. SpyGlass Constraints generates new constraints where needed and verifies that existing constraints are correct and consistent across all phases of development: from pre-synthesis to pre-layout and post-layout.

The SpyGlass Constraints solution can trim weeks or more from design schedules by pinpointing the root cause of constraint problems. By ensuring valid constraints, SpyGlass Constraints can eliminate design flaws and costly re-spins. The solution also creates a smooth handoff between tools in multi-vendor flows. Advanced options streamline constraints management tasks by automating timing exception generation and verification.

Generate and Validate Constraints - Automatically

The SpyGlass Constraints solution automatically generates new constraints from RTL or netlists based on the topology of the design. It identifies clocks, including generated clocks and associates all inputs with the correct clocks. SpyGlass Constraints understands multiplexed inputs, identifies clock domain crossings and generates false path constraints at those crossings. SpyGlass Constraints checks new constraints and legacy constraints against RTL and netlists to verify correctness and completeness at each stage. Consistency is also checked among constraints - between multiple block-level constraints and between block and top-level constraints. SpyGlass Constraints also understands complex case analysis in order to make sure that all modes are addressed within and across constraints files for different modes and corners.

Timing Exception Generation & Verification

SpyGlass Constraints simplifies the difficult task of timing exception management. The Timing Exception Verification (TXV) feature automatically verifies the correctness of exceptions that designers have previously specified. TXV uses sophisticated techniques to examine the netlist to identify timing-critical false and multi-cycle paths.

The Methodology

Atrenta's SpyGlass solution methodology provides a structured, easy to use and a comprehensive method for solving RTL design issues, thereby ensuring high quality RTL with fewer design bugs.

  • Methodology documentation and rule-sets are provided as part of the product
  • Methodology optimizes constraints at the RTL block level, chip level, pre-layout and post-layout stages. The steps include design setup, creation of new SDC constraints, cleaning clock and delay constraints, fixing timing exceptions, resolving hierarchical constraint mismatches and creating timing-critical exceptions after static timing analysis

Features & Benefits

  • Automatically creates and verifies constraints
  • Ensures that constraints are correct and consistent throughout the design flow, from RTL through floorplanning
  • Validates consistency and correctness at all levels: chip-to-block and block-to-block
  • Can save weeks or months of manual creation and verification effort
  • Simplifies management of legacy constraints
  • Supports RTL and netlist input
  • Supports full Tcl-based SDC, compliant with Design Compiler, PrimeTime and BlastFusion constraints formats
  • Flags redundant and over-specified constraints
  • Advanced options automate timing exception generation and verification