SpyGlass® DFT

Design for Test at RTL

SpyGlass® DFT has the unique ability to predict ATPG (automatic test pattern generation) test coverage and pinpoint testability issues as the RTL description is developed, even before a gate-level netlist is generated. The SpyGlass DFT solution not only detects testability issues--it can also automatically correct them. Traditional approaches depend on test engineers to design test clocks and set/reset logic for scan insertion at the gate level, when changes can be difficult, time-consuming and expensive. SpyGlass DFT enables users to tune testability during RTL creation, when the design impact is greatest and the cost of modifications is lowest. This can significantly shorten development time, reduce cost and improve overall quality.

At-speed Testing Support

The test clocks in traditional stuck-at testing are designed to run on the test equipment at frequencies lower than the system speed. At-speed testing requires test clocks to be generated at the system speed, and therefore are often shared with functional clocks from a phase locked loop (PLL) clock source. This additional test clocking circuitry affects functional clock skew, and thus the timing closure of the design. At-speed tests often result in lower than required fault coverage even with full-scan and high (>99%) stuck-at coverage. Identifying reasons for low at-speed coverage at the ATPG stage is too late to make changes to the design and affects schedules significantly. SpyGlass DFT DSM addresses these challenges with advanced timing closure analysis and RTL testability improvements.

Memory Testing Support

Advanced deep submicron designs have hundreds, if not thousands of memories. Testing these memories requires inserting memory built-in self test (MBIST) to achieve high yields. Traditionally, the design is synthesized and then handed over to the ASIC vendor to insert MBIST logic at the netlist level. This approach has several drawbacks:

  • Functional verification takes longer and is not in the control of the system designer
  • Optimization during synthesis/early floor-planning does not take MBIST logic into account
  • BIST sharing schemes and architectural trade-offs could result in many design iterations
  • RTL for the design does not remain golden for IP handoff/reuse

SpyGlass MBIST has the unique ability to insert MBIST at RTL with any ASIC vendor's qualified library and validate the new connections.

Click here to view the SpyGlass MBIST flow

The Methodology

Atrenta's SpyGlass solution methodology provides a structured, easy to use and a comprehensive method for solving RTL design issues, thereby ensuring high quality RTL with fewer design bugs.

  • Methodology documentation and rule sets are provided as part of the product
  • User-guided DFT methodology results in fewer but meaningful violations, thus saving time for the RTL designer
  • Walks users through a series of recommended steps to analyze DFT violations at the block and chip level - the steps include design setup, defining initial test signals, scan wrapping black boxes, using by-pass constraints for modules with internal by-pass logic, achieving scannability, making latches transparent, adding test points, and validating scan chains

Features & Benefits - Design for Test at RTL

  • Pinpoints and diagnoses DFT issues at RTL or gate level
  • Predicts ATPG test coverage with high correlation (within 1% of final ATPG result)
  • Ensures that RTL is scan-compliant
  • Built-in controllability and observability engine analyzes testability strategies
  • Guides selection of highest-value test points
  • Unique AutoFix capability automatically corrects RTL to improve scannability
  • Intuitive, integrated debug environment with cross-probing among views

Features & Benefits - At-Speed Testing Support

  • At-speed test rules help resolve timing closure issues upfront at RTL
  • Predicts at-speed test coverage early at RTL
  • Enables RTL designers to fix design-for-test and timing closure issues upfront without being experts
  • Achieve high at-speed test coverage (>90%) in golden RTL and maintain throughout design implementation

Features & Benefits - Memory Testing Support

  • Accepts BIST IPs from any qualified ASIC/memory vendor
  • Provides an automated process for capturing design-dependent and BIST IP-dependent information
  • Allows multiple RTL insertion capabilities and support various BIST architectures and fuse-wrapper IPs
  • Supports a bottom-up methodology for hierarchical design flow
  • Provides timing constraints (SDC) promotion on the modified RTL for synthesis and test insertion
  • Allows timing-optimization of the complete RTL with BIST logic during synthesis
  • MBIST area impact is known early
  • DFT rules can be run at RTL that include MBIST logic