Slashing the Risk of Complex IC Development

The SpyGlass solution greatly reduces the risk of developing complex multimillion-gate, nanometer-scale ICs, enabling companies to build better products, faster and more economically. The SpyGlass solution accurately detects design issues at the point of creation. In traditional flows, such problems are typically discovered much later, at the gate level, if at all, after much time and expense have been invested in the design. With the SpyGlass solution, designers can optimize designs at RTL, when the ability to make enhancements is greatest and the cost of modifications lowest. And the SpyGlass solution flags areas of the design that are likely to present implementation challenges, so that appropriate resources can be applied to mitigate schedule and complexity risk.

In detecting problems and helping effect their resolution, the SpyGlass solution leverages decades of accumulated design experience.

Structural RTL Checks

The SpyGlass solution integrates a large base of industry-standard best practices, as well as Atrenta's own extensive experience working with industry-leading customers by performing structural checks on RTL design. It includes design reuse compliance checks such as STARC and OpenMORE to enforce consistent style throughout the design, ease the integration of multi-team and multi-vendor IP and promote design reuse. SpyGlass detects synthesizability & simulation issues much before you enter long cycles of verification and implementation. SpyGlass also checks for clock-reset issues in RTL.SpyGlass automates the audit and design review process by producing simple violation and waiver reports.

Advanced Lint

The SpyGlass solution extends linting by using state-of-the-art formal verification techniques to analyze deeper RTL design issues without requiring testbench or assertions. Advanced Lint ensures RTL intent is correct by verifying control logic (FSM), signals toggling, bus integrity (contention, floating state, index overflow) and design initialization. Your RTL is more optimized and verifiable with comprehensive FSM style reporting and detection of logic redundancies (dead code). This improves the area timing, power, testability of your RTL.

The Methodology

Atrenta's SpyGlass solution methodology provides a structured, easy to use and a comprehensive method for solving RTL design issues, thereby ensuring high quality RTL with fewer but meaningful violations.

• Provides methodology documentation and rule-sets as part of the product
• Provides an infrastructure for rule selection and customization aligned with design milestones
• Walks users through a series of recommended steps to ensure design compliance to HDL standards, coding style, synthesis, simulation, verification, connectivity finite-state machine, clock and reset issues
• This step-by-step approach detects and fixes design bugs in alignment with design milestones, and ensures predictable design closure without any last minute surprises or a high volume of violations

• Sophisticated static and dynamic analysis--identifies critical design issues at RTL
• Industry-leading comprehensive clock and reset analysis
• A comprehensive set of electrical rules checks to ensure netlist integrity
• Formal analysis of RTL for FSM correctness, bus contention, dead code and other critical functional issues, without requiring testbench or assertions.
• Customizable framework to capture and automate company expertise
• High performance and capacity to rapidly analyze complex, multimillion-gate designs
• Integrated debug environment enables easy cross-probing among violation reports, schematic and RTL source
• The most comprehensive knowledge base of design expertise and industry-standard best practices
• Supports Verilog, VHDL, V2K, SystemVerilog and mixed-language designs