The benefits are substantial. Traditional approaches depend on test engineers to design test clocks and set/reset logic for scan insertion at the gate level, when changes can be difficult, time-consuming and expensive. The SpyGlass-DFT solution, by contrast, enables users to tune testability during RTL creation, when the design impact is greatest and the cost of modifications lowest. The SpyGlass-DFT solution can significantly shorten development cycles, reduce costs and improve overall testability.


Accurately Predicts Test Coverage at RTL; Extensible DFT Rules

The SpyGlass-DFT solution predicts test coverage at RTL (before synthesis and scan insertion) with extraordinary accuracy: often within 1 percentage point of the final ATPG number. It also helps ensure that the RTL is compliant with the requirements for scan insertion and ATPG.

The SpyGlass-DFT solution includes a comprehensive set of over 100 design-for-test rules. Users can also write their own rules to enforce company-specific DFT practices and policies. The solution features a unique AutoFix ability to automatically correct RTL code for improved scannability.

The SpyGlass-DFT solution includes an intuitive design and diagnostic environment combining RTL design capture and browsing with schematic visualization. Users can easily cross-probe between violation reports, schematics and RTL windows to trace problems to their source and make appropriate changes.

At-speed Testing Problem

The test clocks in traditional stuck-at testing are designed to run on the test equipment at frequencies lower than the system speed. At-speed testing requires test clocks to be generated at the system speed, and therefore are often shared with functional clocks from a phase locked loop (PLL) clock source. This additional test clocking circuitry affects functional clock skew, and thus the timing closure of the design. 

At-speed tests often result in lower than required fault coverage even with full-scan and high (>99%) stuck-at coverage. Identifying reasons for low at-speed coverage at ATPG stage is too late to make changes to the design and affects schedules significantly.

The Methodology

Atrenta's SpyGlass-DFT solution methodology provides easy-to-use and a comprehensive method for solving Design-for-Test problems at RTL to ensure higher test quality

• Provides methodology documentation and rule-sets as part of the product
• The user-guided DFT sub-methodology results in fewer but meaningful violations, thus saving time for the RTL designer
• Walks users through a series of recommended steps to analyze DFT violations at block and chip level - the steps include design setup, defining initial test signals, scan wrapping black boxes, using by-pass constraints for modules with internal by-pass logic, achieving scannability, making latches transparent, adding test points, and validating scan chains

• Pinpoints and diagnoses DFT issues at RTL or gate level
• Predicts ATPG test coverage with high correlation (within 1% of final ATPG result)
• Pinpoints causes that block high at-speed coverage
• Ensures that RTL is scan-compliant
• Built-in controllability and observability engine analyzes testability strategies
• Guides selection of highest-value test points
• Unique AutoFix capability automatically corrects RTL to improve scannability
• Intuitive, integrated debug environment with cross-probing among views

SpyGlass-DFT DSM
The product option introduces advanced timing closure analysis and RTL testability improvement for deep submicron (DSM) defects associated with at-speed testing.

	SpyGlass-DFT DSM Diagnostics for Low Coverage Click here to view the larger version		Key Features At-speed test rules help resolve timing closure issues upfront at RTL Predicts at-speed test coverage early at RTL Pin-points and diagnoses low coverage issues at RTL Key Benefits Enables RTL designers to fix design-for-test and timing closure issues upfront without being experts Address testability early in RTL without having to spend days later in the design cycle Achieve high at-speed test coverage (>90%) in golden RTL and maintain through out design implementation

Advanced deep submicron designs have hundreds, if not thousands of memories. It is required to test the memories in the design by inserting memory built-in self test (MBIST) to get high yields.
Traditionally, designers synthesize the design first to a gate level representation and then hand it over to the ASIC vendor to insert MBIST logic at the netlist level.

When MBIST is inserted at the gate level:
- Functional verification takes longer and is expensive is not in control of the system house/designer
- Optimization during synthesis/early floor-planning does not take MBIST logic into account
- BIST sharing schemes and architectural trade-offs could result in many design iterations through RTL synthesis and floor planning
- RTL for the design does not remain golden for IP handoff/reuse

Designers need a RTL solution that is flexible and easily integrates with any vendor's BIST IPs and provides automation for BIST insertion at RTL.

SpyGlass-MBIST
Vendor Independent RTL MBIST Solution
The SpyGlass-MBIST product has the unique ability to insert MBIST at RTL with any ASIC vendor's qualified library and validate the new connections.

Click here to view the SpyGlass-MBIST flow
Features

• Accepts BIST IPs from any qualified ASIC/memory vendor
• Provides an automated process for capturing design-dependent and BIST IP-dependent information
• Allows multiple RTL insertion capabilities and support various BIST architectures and fuse-wrapper IPs
• Supports a bottom-up methodology for hierarchical design flow
• Provides timing constraints (SDC) promotion on the modified RTL for synthesis and test insertion
• Allows a "Dummy design" capability to preserve RTL confidentiality when system house wants to hand over the netlist with BIST for validation at ASIC vendor's site

• Allows earlier and faster validation than at gate level as simulations are run at RTL
• Allows timing-optimization of the complete RTL with BIST logic during synthesis
• MBIST area impact is known early
• DFT rules can be run at RTL that include MBIST logic
• MBIST insertion/validation automation allows:
  • BIST insertion to be transparent to the user like scan insertion
  • Less error prone compared to manual approach resulting in improvement of design integration quality
  • Predictable & provides reproducible results to control design schedule
  • Allows easy exploration of different MBIST strategies to find the best BIST system