SpyGlass®-Physical

RTL designers need to make decisions that impact the power, timing and physical feasibility of a chip during the downstream implementation flow. Since RTL designers have limited visibility into physical implementation, the impact of these decisions are resolved late in the process. The result can be several iterations between back-end and front-end designers, a costly problem.

SpyGlass-Physical provides early estimates of area, power, timing and routability for RTL designers without the need for physical design expertise or tools. For the RTL leads and SoC integrators, it evaluates multiple floorplan configurations, analyzes implementation feasibility, enables appropriate IP selection, creates physical partitions and generates implementation guidance for IP and SoC implementation.

With SpyGlass-Physical, RTL designers can make sure RTL blocks will be easier to implement and will meet SoC design goals.

Key Features

• Provides a design dashboard with early estimates of RTL block power, timing, and congestion which is easy to understand for RTL designers and managers
• Enables critical area, power, timing and congestion trade-offs early in the design phase
• Provides rich visualization, interactivity and reporting to determine physical feasibility
• Provides quick and accurate what-if analysis of architecture and micro-architecture both at IP and SoC level
• Provides accurate and fast what-if analysis of multiple floorplan configurations
• Generates floorplan and constraints guidance for IP and SoC development
• Provides partitioning of physical blocks to meet SoC targets quickly
• Support for connectivity abstractions such as interface definitions and transaction specification
• Extremely easy to use for RTL designers, RTL lead and SoC integrators
• Very fast analysis to enable multiple iterations within a day

Key Benefits

• Provides relative quantitative measure of implementation readiness of RTL blocks - Facilitates tracking block implementation readiness progress as part of regression setup
• Very fast analysis to enable multiple iterations within a day leads to faster design closure
• RTL designers can take corrective action based on Rules and PACT reports without having to learn physical aspects or develop tool expertise
• Integrated into SpyGlass platform - Offer physical rules like other SpyGlass tools
• Rich set of visualization, what-if analysis, reports and metrics enable easy to use floorplanning for complex IP and SoC's
• SpyGlass-Physical makes existing flows more efficient and significantly reduce overall design closure time