Early Implementation Readiness Analysis for RTL Blocks
RTL designers need to make decisions that impact the timing and physical feasibility of a chip during the downstream implementation flow. Since RTL designers have limited visibility into physical implementation, the impact of these decisions are resolved late in the process. The result can be several iterations between back-end and front-end designers, a costly problem.
The SpyGlass® Physical solution provides early estimates of area, timing and routability for RTL designers without the need for physical design expertise or tools. It provides high value physical reports and rules to identify area, congestion and timing issues at the early stages of the design. With SpyGlass Physical, designers can make sure RTL blocks will be easier to implement and reduce SoC design closure time.
Features & Benefits
- Provides early estimates of RTL block area, timing and congestion
- Analyzes RTL for area, congestion and timing issues that are otherwise detected late in the implementation cycle
- Cross probes RTL/schematic to facilitate debug
- Uses the same SpyGlass platform to analyze physical issues which is used for linting, CDC, DFT, power and constraints
- Provides ways to track changes in area, congestion and timing as RTL is developed
- Provides fast analysis to enable multiple iterations within a day leading to faster design closure
- Provides a relative quantitative measure of implementation readiness of RTL blocks for design managers
- Enables RTL designers to take corrective action based on rules and reports without having to learn physical aspects or develop tool expertise
- Integrates into the SpyGlass platform - leverages other SpyGlass checks to offer a complete physical analysis flow
- Easier to adopt for RTL engineers
- Provides a rich debugging environment including cross probing to RTL/schematic enabling easier fixing of RTL for implementation readiness
- Makes existing flows more efficient and significantly reduces overall design closure time