SpyGlass® Power

Design for Low Power at RTL

With the SpyGlass® Power solution, users can tune their designs for power consumption and efficiency at the register transfer level (RTL). The SpyGlass Power solution provides early information about power consumption at RTL, and provides guidance where power can be reduced. SpyGlass Power not only detects, but can also automatically fix key power management issues and formally prove the changes are correct. SpyGlass Power also estimates power consumption at RTL, with or without simulation vectors. To complete the flow, SpyGlass Power verifies power intent in the form of UPF or CPF.

Traditional approaches address power analysis and optimization at the gate level, making changes difficult and costly and complicating verification. The SpyGlass Power solution, in contrast, enables users to tune power characteristics during RTL creation, when the design impact is greatest and the cost of modification is lowest. The result is a shortened development cycle, reduced cost and improved power consumption of the finished product.

Verify, estimate and reduce - SpyGlass Power does it all.

Low Power Guidance

Using circuit activity data from simulation, the SpyGlass Power solution minimizes dynamic power by ensuring the most effective RTL clock gating strategy. It also includes a complete set of power reduction techniques addressing data path controls, clocks, buses and memory units.

SpyGlass Power also helps users manage the complexity of multiple power and voltage domains - they can verify, visualize and analyze multiple domains and domain crossing issues. SpyGlass Power includes an intuitive design and diagnostic environment combining RTL design capture and browsing with schematic visualization. Users can easily cross-probe between violation reports, schematics and RTL windows to trace problems to their source and make appropriate changes.

The Methodology

Atrenta's SpyGlass solution methodology provides a structured, easy to use and a comprehensive method for solving RTL design issues, thereby ensuring high quality RTL with fewer design bugs.

  • Methodology documentation and rule-sets are provided as part of the product
  • The user is taken through a series of recommended steps to estimate power, reduce power, and ensure the design complies with the power intent defined in UPF or CPF formats

Features & Benefits

  • Estimates power at RTL and gate-level
  • Reduces power - dynamic analysis for clock gate insertion
  • Guides optimal power design at RTL
  • Analyzes power issues at the block and chip levels- RTL or gate level netlist
  • Verifies, visualizes and analyzes voltage and power domain management
  • Verifies that voltage level shifters and isolation logic are correct
  • Intuitive, integrated debug environment with cross-probing among views
  • Supports UPF and CPF power formats