Early Design Analysis for Logic Designers (Lint)

Using advanced static analysis, Base SpyGlass pinpoints structural, coding and consistency problems in RTL descriptions. The SpyGlass Lint solution offers a comprehensive solution for analysis of RTL structures. It traces problems to their source and helps designers resolve issues before they creep into downstream design implementation. The SpyGlass platform also addresses electrical rules checking (ERC) in the design. 

Structural RTL Checks

Base SpyGlass linting integrates industry-standard best practices, as well as Atrenta's own extensive experience working with industry-leading customers. Lint checks include design reuse compliance checks such as STARC and OpenMORE to enforce a consistent style throughout the design, ease the integration of multi-team and multi-vendor IP and promote design reuse. Base SpyGlass detects synthesizability & simulation issues way before the long cycles of verification and implementation. SpyGlass automates the audit and design review process by producing simple violation and waiver reports.

The Methodology

Atrenta's SpyGlass solution methodology provides a structured, easy to use and a comprehensive method for solving RTL design issues, thereby ensuring high quality RTL with fewer design bugs.

  • Methodology documentation and rule-sets are part of the product
  • Provides an infrastructure for rule selection and methodology customization aligned with design milestones
  • Walks users through a series of recommended steps to ensure design compliance to HDL standards, coding style, synthesis, simulation, verification and connectivity requirements
  • Provides an environment to detect and fix design bugs in alignment with design milestones, and ensures predictable design closure without any last minute surprises or a high volume of violations
  • Creates a concise DashBoard of the analysis results to track the progress of design quality

Features & Benefits

  • Sophisticated static and dynamic analysis--identifies critical design issues at RTL
  • A complete set of electrical rules checks to ensure netlist integrity
  • Customizable framework to capture and automate company expertise
  • High performance and capacity to rapidly analyze complex, multimillion-gate designs
  • Integrated debug environment enables easy cross-probing among violation reports, schematic and RTL source
  • The most comprehensive knowledge base of design expertise and industry-standard best practices
  • Supports Verilog, VHDL, V2K, SystemVerilog and mixed-language designs
  • Tcl shell for efficient rule execution and design query
  • SoC abstraction flow for faster performance and low noise