Today's large SoC design economics has forced design teams to have a separate implementation and integration team. This team typically receives a RTL level hand-off from various RTL design groups along with constraints. The team is chartered to perform logic synthesis, testability analysis, insertion and static-timing-analysis. These teams are typically responsible for integrating various blocks to produce full-chip level netlist. This team also does hand-offs to place and route team. There can be variations of this theme specific to a project.

The implementation team is challenged with multiple diverse RTL hand-offs and constraint files. There usually is no consistency in the quality of these hand-offs from various RTL teams. The implementation team is saddled with discovering many issues like synthesizability, testability, power dissipation and inter-block interaction etc. These issues need to be communicated to RTL teams. When the issues are remedied by RTL team, a re-processing of data-bases takes place. These iterations are unpredictable, costly and time consuming. Sometimes the design intent is lost in these iterations leading to back-end slips of schedules. It also delays the hand-off of the full netlist for place and route. Most importantly these iterations are unpredictable and can cause significant schedule delays when the design is finally closed.

Atrenta products and methodologies can ensure that the required correctness is built in to the RTL code. In other words, certain issues are closed early at RTL authoring stage before hand-off. Atrenta products can also allow verification engineers to evaluate the quality of RTL code hand-off without elaborate tool runs. Implementation engineers can quickly assess (or insist assessment at RTL authoring stage before hand-off) for issues as follows:

• Syntesizability issues
• Gate level to RTL mismatches
• Power saving opportunities
• Test coverage and testability improvement opportunities
• Completeness and coherency of constraint files that drive expensive synthesis and timing verification runs
• Attributes and characterization of third party IP
• Interblock combinational paths and clock domain crossing issues
• Voltage island isolation and usage of correct isolator and level shifter cells
• Gate count and die size estimates before embarking on runs of exhaustive tool set
• Possible deep cone logic constructs leading to critical paths in the design