With today's complex SoC systems, verification engineers are faced with the daunting challenge of verification of increasingly large portions of logic within aggressive schedules. Due to size of the chips, multiple geographically diverse groups of RTL designers and IP suppliers provide components of the chip at different times. Multiple iterations are spent in discovering and closing 1st level issues which could have been closed right at RTL authoring stage.

Latency of bug discovery and probability of bug discovery are another two areas of concern for verification engineers. As an example, bugs in the areas of clock domain crossing and synchronizations are extremely difficult to catch. Long, constrained random test sequences might be required to catch certain type of synchronization issues. There are many cases in the industry where these bugs have led to costly silicon re-spins.

Atrenta products and methodologies can ensure that the required correctness is built in to the RTL code. In other words, certain issues are closed early at RTL authoring stage before hand-off. Atrenta products can also allow verification engineers to evaluate the quality of RTL code hand-off without elaborate simulations and test sequences.

Verification engineers can quickly assess (or insist assessment at RTL authoring stage before hand-off) for issues as follows:

• The state machines have no unreachable or uninitializable states
• FIFOS in the design will not underflow or overflow
• Gray encoding is used appropriately during clock domain crossing
• Proper handshakes are implemented for clock domain crossing signals
• Gate level netlist simulation results would match those of RTL simulations
• Tristate busses (if present) have no conflicts due to multiple drivers active at the same time
• All the false paths are correctly accounted for all the modes of operation
• Reset schemes are complete and are guaranteed to reset the chip within certain cycles
• Standard OVL assertions if used are already proven
• Third party IP is screened for all of the above issues. This is of great help if the IP is an encrypted gate level netlist
• Voltage island isolators are properly instantiated for multi-voltage designs