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 Solutions Workshops SpyGlass Constraints Workshop
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| Atrenta Workshop |
| SpyGlass® Constraints - Constraints Analysis Hands-On Workshop |
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Course Description
SoC development involves the validation of constraints at various stages, such as RTL, pre-layout and post-layout. Resolving constraint inconsistencies between the block and chip levels, between synthesis, pre-layout, and post-layout is highly critical for the timely development of SoC and superior quality of the results. This workshop demonstrates how SpyGlass Constraints can help achieve the goal of predictive development of your SoC designs.
Agenda - How Constraints Cause Heart-Burn Today
- Introduction to SpyGlass Constraints
- Checks in SpyGlass Constraints
- Advanced Features in SpyGlass Constraints
- Where to Look for More Information
Hands-On Exercise Attendees will work with a design at RTL. The attendees will run the following analysis on this design: - Constraints Consistency and Completeness Checks at the Block-Level RTL
- Constraints Checks at the Top/Chip Level
- Incremental SDC generation
- Pre-Layout and Post-Layout Netlist Constraint Checks
- SDC Equivalence Checks
Duration 1/2 day Prerequisites Prior experience with Synopsys Design Constraints (SDC); working knowledge of hardware description languages, such as Verilog and/or VHDL; prior experience with SpyGlass Predictive Analyzer. Target Audience Synthesis and Timing Analysis Experts, Design Validation Engineers, and Design Methodology Engineers.
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