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Course Description:
This workshop introduces users to the predictive analysis capability of SpyGlass. The use of SpyGlass in the various methodologies in the RTL handoff process such as audit, block-design
and RTL-handover are explained in this workshop.
Agenda:
- SpyGlass Overview
- The GuideWare™ methodology for continuous
design analysis
- GuideWare setup and configuration
- Q and A
- SpyGlass Predictive Analysis Labs
Hands-On Exercise Attendees will work with a ~200K RTL design which is a collection of IP blocks that have been assembled together.
The attendees will run the following analysis on this design. - GuideWare-based analysis overview of a sample design
- GuideWare analysis of a new RTL block
- GuideWare analysis of an IP block
Duration: 1/2 day
Pre-Requisites:
Comfortable knowledge in hardware description languages like Verilog and/or VHDL, knowledge in Perl is useful but not essential.
Targeted Audience: Design/project managers, RTL designers, design methodology engineers, back-end implementation engineers,
IP/SoC design/verification engineers.
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