Course Description

This workshop introduces the clock and reset analysis capabilities in SpyGlass-CDC for use in clock domain crossing (CDC) analysis. The workshop covers the following topics:

• The Analysis of CDC Using Standard Synchronization Schemes, Such as 2-Flop, Common Mux Enable
• The Analysis of Common Issues in the Design, Such as Potential Race Conditions and Clock Glitches
• How to Visualize Clock and Reset Trees in the Design
• How to Debug the Design Using Parameters in SpyGlass

Agenda:

• Clock-Reset Analysis ? Why is it Important?
• Methodology to Use
• Templates in Clock-Reset Policy
• Inputs Required for SpyGlass-CDC
• What are Clock Domain Crossings ? Importance
• Synchronizations Schemes Detected by SpyGlass
• Advanced CDC Verification Capabilities for Reconvergence, FIFOs and Handshakes

Hands-On Exercise

Attendees will work with a ~200K RTL design. This design is a collection of IP blocks that have been assembled together. Users will work on correcting the design problems in this design based on the feedback and reports generated by the tool.

Duration

1/2 day

Prerequisites

Knowledge of Digital Designs, including meta-stability, race conditions, glitches, and commonly used synchronization schemes; working knowledge of hardware description languages, such as Verilog and/or VHDL; prior experience with SpyGlass Predictive Analyzer.

Target Audience

RTL Designers, Design Methodology Engineers, Chip Architects, and IP/SOC Design/Verification Engineers.

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