This training focuses on Power Estimation, Power Reduction and Power Verification aspects of design to ensure extremely power-efficient designs.

This training demonstrates the ability to estimate power early at RTL with different what-if analysis scenarios . Training will also walk you through several power optimization approaches and explore the challenges of "getting it right". Topics such as: over-looked enables, inefficient clock enables, wasted data path activity, missing circuitry, power & voltage domain definition and managing multiple power intent across the different stages of the design will be discussed. Real design examples will be used to illustrate these challenges.

Agenda

• Atrenta Overview
• Introduction to Power issues
• SpyGlass Recommended Power Flow and Methodology
• Power Estimation and Activity Analysis
• Power Reduction
• Power Verification ?RTL and Post Synthesis / Post Layout

Hands-On Exercise

Attendees will work with a ~200K RTL design which is a collection of IP blocks that have been assembled together. This design will be used to perform following analysis:

• Working with Power Estimation
• Working with Power Reduction
• Working with Power Verification

Duration

1 day

Prerequisites

Knowledge of digital design and low power techniques and guidelines; working knowledge of hardware description languages such as Verilog and/or VHDL; prior experience with SpyGlass Predictive Analyzer is required. Knowledge of PERL is useful but not essential.

Target Audience

Low Power Designers [Chips for Wireless/Handheld Applications, Consumer Electronics]; SOC Architects with a power budget; RTL Designers, Design Methodology Engineers, Implementation Engineers, Chip Architects, and Design Validation Engineers.