Course Description
SoC development involves use of design constraints (SDC) at various design stages. Incorrect or missing exceptions among the constraints lead to sub-optimal QoR in
terms of area, timing or power. Most importantly, incorrect timing exceptions may lead to silicon timing failure. This workshop demonstrates how SpyGlass-Constraints Timing Exception
Verification (TXV) can help to functionally verify the false path exceptions in your SoC designs.
Agenda - How Timing Exceptions Cause Problems
- Timing Exception Validation Concepts
-
Introduction to TXV False Path/Multi-cycle path Verification
- Steps to verify False/Multi-cycle paths in TXV
- Generation of assertions to aid verification
- Timing critical false/multi-cycle path generation from STA
- Where to Look for More Information
Hands-On Exercise
Attendees will work with a ~200K RTL design which is a collection of IP blocks that have been assembled together.
The attendees will run the following analysis on this design. - Sanity Check Up for Design Constraints Before False Path Verification
- Verify False Paths
- Debug False Path Verification Results
- Generate a set of timing-critical false paths
Duration 1/2 day Prerequisites Prior experience with Synopsys Design Constraints (SDC); working knowledge of hardware description languages, such as Verilog and/or VHDL; prior experience with SpyGlass Predictive Analyzer Target Audience RTL designers, Synthesis and Timing Analysis Experts, Physical Design Engineers, and Design Methodology Engineers. Request additional information | 
