Low Power Design: Approach and Techniques for Power Estimation, Reduction and Verification

Power dissipation is a major concern in modern day IC design. For wireless electronic appliances, battery life is one of the major influencers of the purchase decision and can be an effective differentiator. Mobile phones, PDAs, digital cameras and personal MP3 players are increasingly being sold on the long battery lives...

Designing for Test at RTL

Design for test (DFT) techniques impose rigorous and generally well-known constraints on a design. These constraints include issues with respect to clock generation and distribution, asynchronous sets and resets, memory controls and tristate busses...

Estimating Fault Coverage from RTL without Fault Simulation

This paper describes a method for estimating fault coverage from register transfer level (RTL) descriptions of complex circuits. The method does not require test benches or the use of fault simulation and therefore offers the advantage of very rapid turnaround with no additional user effort.

Facilitating At-speed Test at RTL

This white paper demonstrates a solution for facilitating at-speed test at the register-transfer level. The RTL approach is important, because designers and test engineers usually verify the test coverage only at the gate level during the final ATPG stage. This RTL solution thus saves weeks of effort by fixing potential issues up front.

Do your Chip a Favor! Manage the Constraints!!

Design goes through several transformations in a typical RTL-to-layout flow. There are several verification steps in place to make sure that the design intent has not changed. For example, simulation, equivalence checking and so on. In practice, Timing Constraints are created at RTL level just as RTL is created and are refined throughout the design cycle...

Improved Timing Closure through Constraint Checking

At 90nm, design verification, a critical chip design process task, takes up to 70% of the design time and reducing this time would greatly lower the final product cost resulting in significant advantage in time-to-profit. This paper investigates some problems associated with constraints and offers ways to identify them early in the design process, thus shortening timing closure…

Constraints Management: Approach and Techniques for Preserving the Intent of Timing Constraints throughout the Design Flow

Constraints management is a major concern for designers today and increasing design complexity, coupled with mounting time to market pressure, makes faster timing closure and reduced iterations a necessity. Any late stage constraint change brings with it enormous costs, both in terms of time and money, and can lead to a failed design project.

Combining Structural and Functional Verification Techniques to Improve Effective CDC Verification

Multiple, independent clocks have become a fact of life on SoCs and other complex ASICs. In extreme cases, such as in large communications processors, clock domains may number in the thousands. Clock domain crossings pose a growing challenge to chip designers...

Managing and Measuring RTL Development Progress: Optimizing the Complete Design Flow

In recent years the impact of "bad RTL" has grown as designs have become more complex and code reuse has become commonplace in the mainstream design flow. There are many contributing factors, such as lack of adequate testing and frequent design changes within sufficient re-validation...

Atrenta Predictive Development

Creating complex electronic systems has never been easy, but in recent years it has become truly daunting. It now takes an average of $40 million to develop a system-on-chip (SoC), a big risk even for the largest companies. Missteps can drive the expense up further.

Total Quality Management: Manual Systems aren't Enough

The drive toward better total quality management (TQM)is gaining momentum in many high-tech industries, from software to hardware development and beyond. In fact, TQM is likely to become a key competitive differentiator in arenas such as embedded software...