Atrenta's Design Closure Stimulus Package seminars have been designed to assist chip companies to build better products, both faster and more economically, by detecting and mitigating design risks earlier in the design process than ever before. Atrenta will visit major semiconductor hubs around the world to share the latest technologies and methodologies for Early Design Closure®.

Presented by the company's technology experts, these seminars will be aimed primarily at engineering managers, chip architects, RTL designers, design methodology engineers and IP design/verification engineers seeking to implement correct designs rapidly through the integrated use of a variety of design automation solutions. The free seminars, typically scheduled for 90 to 120 minutes during lunch, will cover a variety of topics, including clock domain crossing verification, design for test, constraints analysis, power management, modeling of physical effects at RTL and platform-based design techniques. Detailed case studies will demonstrate how to improve methodologies and achieve better Early Design Closure.

• Faster, Safer Timing Closure through Better Constraints, Jun 25, 2009 in California
  
• Eliminate Power Bugs & Hogs, Mar 18-19, 2009 in Southern California
  
• Eliminate Power Bugs & Hogs, Thurs, Feb 5, 2009 in Santa Clara, USA
  
• Catching CDC & DFT Bugs, Thurs, Jan 29, 2009 in Noida, India, and Mon, Feb 2, 2009 in Bangalore, India
  

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