Course Description: This workshop introduces users to the predictive analysis capability of SpyGlass. The use of SpyGlass in the various methodologies in the RTL handoff process such as audit, block-design and RTL-handover are explained in this workshop.
Agenda: - SpyGlass Overview
- Using SpyGlass for Block Design
- RTL Handover methodology as part of Design Exploration
- Design Exploration
- DFT Methodology
- Other Methodologies
- Language-Specific features
- Controlling SpyGlass Analysis
- Q and A
- SpyGlass Predictive Analysis Labs
Duration: 1 day
Pre-Requisites: Comfortable knowledge in hardware description languages like Verilog and/or VHDL, knowledge in Perl is useful but not essential.
Targeted Audience: Design/project managers, RTL designers, design methodology engineers, back-end implementation engineers, IP/SoC design/verification engineers.
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