This workshop demonstrates the testability analysis capabilities of SpyGlass-DFT to be used in the RTL hand-off process, using a combination of design methodology templates and interactive debugging available within SpyGlass. It explains how the fault-coverage can be enhanced based on the recommendations from SpyGlass-DFT. The workshop will review how to make all the flops scannable, all latches transparent and improve testability of the design.

Agenda

• Introduction to SpyGlass-DFT
• Using Constraints for DFT Analysis
• SpyGlass-DFT RTL Autofix
• DFT Templates: How to Run DFT Analysis
• Diagnostic Techniques for DFT Analysis
• Where to Look for More Information

Hands-On Exercise

Attendees will work with a design at RTL which has several design and testability problems. The goal of the exercise is to enhance the fault-coverage to an acceptable level (>95%) following the recommendations from SpyGlass-DFT.

Duration

½ day

Prerequisites

Working knowledge of hardware description languages such as Verilog and/or VHDL, and prior experience with SpyGlass Predictive Analyzer is required. Knowledge of PERL/TCL is useful but not essential. Prior experience with Atrenta SpyGlass tool is useful.

Target Audience

This training is intended for RTL designers who hand-off the designs to the test engineers.