This workshop focuses on voltage and activity management as well as best design practices to ensure extremely power-efficient designs.

Voltage and activity management opens up a whole new dimension to low-power design methodology. Although, the ideas of using multiple power domains or shutting down idle portions of the design are simple, they are immensely powerful as well. SpyGlass-Power utilizes these ideas and several such practices to embed power efficiency in the design process itself, thereby ensuring low power, by design. This workshop also takes an in-depth look at the switching activity analysis to enable intelligent clock gating.

Agenda

• Low Power Design
• RTL Power Estimation
• Power Reduction: Activity Analysis
• Power Reduction: Additional LP Best Practices Rules
• Power Verification: Voltage Management

Hands-On Exercise

Attendees will work with a ~200K RTL design which is a collection of IP blocks that have been assembled together. This design will be used to perform following analysis:

• Working with Voltage and Power Managed Designs
• Working with Activity Analysis
• Working with Best Practices for Low Power Design

Duration

1/2 day

Prerequisites

Knowledge of digital design and low power techniques and guidelines; working knowledge of hardware description languages such as Verilog and/or VHDL; prior experience with SpyGlass Predictive Analyzer is required. Knowledge of PERL is useful but not essential.

Target Audience

Low Power Designers [Chips for Wireless/Handheld Applications, Consumer Electronics]; SOC Architects with a power budget; RTL Designers, Design Methodology Engineers, Implementation Engineers, Chip Architects, and Design Validation Engineers.