Techniques for FSM Design and Verification, SpyGlass Advanced Lint
Large system-on-chip (SoC) designs contain many finite state machines (FSMs), which combine with data paths, memories, and other components. FSMs are sources of functional bugs in SoCs. Designers often attribute poor timing, power, and performance to poor FSM design. Although verification tools can perform checks on FSMs, such as deadlock and unreachable states, these tools may not consider all aspects of FSM design styles.
In this White Paper we will discuss FSM functional issues, metrics, design styles, and systematic validation approaches.
Lint Your Hardware Description: The Need to be Fast, Accurate, Scalable and Flexible, SpyGlass Advanced Lint
A reliable linting tool must be SAFE (Scalable, Accurate, Fast and Extendible) so it can help catch issues early in the design cycle â€“ issues that may be missed by traditional dynamic verification techniques. The main objective of a SAFE linting solution is to reduce costly design iterations, prevent late stage design ECOs and promote seamless reuse of IPs. Such a linting solution will need to co-exist with dynamic verification tools to complete the verification eco-system.