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CDC Verification of Billion Gate SoCs

CDC Verification of Billion Gate SoCs

Abstract
Driven by growing design sizes and complexities and aggressive power requirements, design and verification engineers are witnessing an explosion in the number of asynchronous clocks. Consequently, design and verification teams spend a huge amount of time verifying the correctness of asynchronous boundaries on the chip. The paper describes three methodologies to address this issue and the benefits of each.

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SpyGlass CDC
SpyGlass Flow for XILINX FPGA

SpyGlass Flow for XILINX FPGA

Abstract
SpyGlass Lint and CDC are critical analysis tools for RTL designs that identify chip killer problems and shorten design cycle time. This document highlights the issues that come up when taking a XILINX FPGA-based design through the default SpyGlass flow. With a script-ware based approach, the work required to make the design SpyGlass compatible is significantly reduced. The approach takes care of handling Xilinx library files, design files and design constraints.

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SpyGlass CDC
Combining Structural and Functional Verification Techniques to Improve Effective CDC Verification

Combining Structural and Functional Verification Techniques to Improve Effective CDC Verification

Abstract
Multiple, independent clocks have become a fact of life on SoCs and other complex ASICs. In extreme cases, such as in large communications processors, clock domains may number in the thousands. Clock domain crossings pose a growing challenge to chip designers

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SpyGlass CDC
Verification of Multi-Clock Designs - The Bigger Picture

Verification of Multi-Clock Designs - The Bigger Picture

Abstract
This white paper outlines a holistic approach to resolving issues associated with ever increasing numbers of clock interfaces, where data is transferred between clocks of different frequencies and often between asynchronous domains. The paper suggests exercising various technologies as part of an intuitive user environment, and highlights why addressing one issue in isolation can at best jeopardize timing closure, and at worst introduce silicon risk.

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SpyGlass CDC
Understanding Formal Verification Concepts - Part 1

Understanding Formal Verification Concepts - Part 1

Abstract
This paper describes formal verification concepts and the differences between formal and simulation techniques, especially in the context of assertion-based verification. The assertion- based verification flow and some of the formal verification algorithms are also discussed in detail. Last but not the least, a few applications of formal technology in the context of ASIC designs are also listed.

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SpyGlass CDC
Understanding Formal Verification Concepts - Part 2

Understanding Formal Verification Concepts - Part 2

Abstract
In this second white paper in a three-part series about formal verification concepts, we examine the assertion-based verification flow and some of the formal verification algorithms. This kind of approach has become necessary as SoC designs become more challenging and as the traditional method of simulation proves too slow, too costly, and insufficient in terms of coverage.

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SpyGlass CDC
Understanding Formal Verification Concepts - Part 3

Understanding Formal Verification Concepts - Part 3

Abstract
In this final white paper in a three-part series about formal verification concepts, we examine the assertion-based verification flow and some of the formal verification algorithms.

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