This white paper demonstrates a solution for facilitating at-speed test at the register-transfer level. The RTL approach is important, because designers and test engineers usually verify the test coverage only at the gate level during the final ATPG stage. This RTL solution thus saves weeks of effort by fixing potential issues up front.
Design for test (DFT) techniques impose rigorous and generally well-known constraints on a design. These constraints include issues with respect to clock generation and distribution, asynchronous sets and resets, memory controls and tristate busses.
Analysis of Random Resistive Faults and ATPG Effectiveness at RTL, SpyGlass DFT
Traditional netlist-based DFT analysis runs into design rule violations during scan insertion in synthesis and needs RTL designers to modify the design for uncontrollable clocks and resets. Similarly, low fault coverage during ATPG results in designers having to modify RTL to improve observability and controllability causing many design iterations and schedule impact.
This paper describes a method for estimating fault coverage from register transfer level (RTL) descriptions of complex circuits. The method does not require automatic test pattern generation (ATPG) or the use of fault simulation and therefore offers the advantage of very rapid turnaround with no additional user effort. An important benefit is the means for a user to quickly determine the change in fault coverage while considering various changes to a design. The technique automatically takes advantage of available designed in test logic and may be applied to either combinational or sequential test generation tools.