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| White Papers : SpyGlass |
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| SpyGlass Application in an FPGA to ASIC Conversion |
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| Abstract |
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| Mapping an FPGA design to an ASIC can be a problem-free experience if the FPGA was designed from the outset with a re-map in mind. If you did not take this precaution, you may find that so many changes are required to make the FPGA RTL ASIC-compliant that you must effectively re-design and re-verify the RTL. In this case, the FPGA implementation becomes little more than an existence proof that a working implementation can be built. By following the Atrenta GuideWare? methodology using the SpyGlass? family of tools, you can achieve portability of the design from the FPGA implementation to the ASIC implementation, and from one process node to the next. Atrenta?s GuideWare methodologies contain a comprehensive set of checks and qualified templates that allow for maximal portability of the design. |
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