| White Papers : SpyGlass-Constraints |
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| Constraints Management: Approach and Techniques for Preserving the Intent of Timing Constraints throughout the Design Flow |
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| Abstract |
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| Constraints management is a major concern for designers today and increasing design complexity, coupled with mounting time to market pressure, makes faster timing closure and reduced iterations a necessity. Any late stage constraint change brings with it enormous costs, both in terms of time and money, and can lead to a failed design project. |
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| Verification of Multi-Clock Designs |
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| Abstract |
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| This white paper outlines a holistic approach to resolving issues associated with ever increasing numbers of clock interfaces, where data is transferred between clocks of different frequencies and often between asynchronous domains. The paper suggests exercising various technologies as part of an intuitive user environment, and highlights why addressing one issue in isolation can at best jeopardize timing closure, and at worst introduce silicon risk. |
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| Do your Chip a Favor! Manage the Constraints!! |
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| Abstract |
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| Design goes through several transformations in a typical RTL-to-layout flow. There are several verification steps in place to make sure that the design intent has not changed. For example, simulation, equivalence checking and so on. In practice, Timing Constraints are created at RTL level just as RTL is created and are refined throughout the design cycle...
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