| White Papers : SpyGlass-DFT |
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| A Register Transfer Level Approach to Memory Built-in Self Test and Repair Insertion |
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| Abstract |
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| This white paper describes a novel approach for memory built-in self test (MBIST) and repair insertion at the register transfer level (RTL). The approach is independent of BIST IP technology and works with any supplier?s qualified ASIC design kit and BIST libraries. The methodology describes both a bottom up and a top down approach to SoC design and validation ? all at the RTL stage. Application of this approach on real industrial designs indicates enhancement of design productivity and shorter cycle time for functional validation. |
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| Facilitating At-speed Test at RTL |
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| Abstract |
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| This white paper demonstrates a solution for facilitating at-speed test at the register-transfer level. The
RTL approach is important, because designers and test engineers usually verify the test coverage only at
the gate level during the final ATPG stage. This RTL solution thus saves weeks of effort by fixing potential
issues up front. |
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| Designing for Test at RTL |
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| Abstract |
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| Design for test (DFT) techniques impose rigorous and generally well-known constraints on a design. These constraints include issues with respect to clock generation and distribution, asynchronous sets and resets, memory controls and tristate busses...
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| Estimating Fault Coverage from RTL without Fault Simulation |
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| Abstract |
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| This paper describes a method for estimating fault coverage from register transfer level (RTL) descriptions of complex circuits. The method does not require test benches or the use of fault simulation and therefore offers the advantage of very rapid turnaround with no additional user effort.
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