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  Atrenta's Worldwide Design Closure Stimulus Package Seminar Series
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Verification of Clock Domain Crossing in SoCs: Part Two—SoC Characteristics - Jun 25, 2009
STMicroelectronics' design kit has memory BIST/repair - Jun 22, 2009
Atrenta SpyGlass®-MBIST Adopted by STMicroelectronics for RTL Memory BIST and Repair Insertion - Jun 11, 2009
Verification of Clock Domain Crossing in SoCs: Part One - Tools and Needs - May 21, 2009
Hear about Atrenta’s efforts to improve IP quality - May 03, 2009
Mike Gianfagna speaks at DesignCon 2009 - By EDACafe - Feb 24, 2009
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DAC 2009
Booth# 1528, South Hall
Jul 27-30, 2009
San Francisco
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