SpyGlass Platform

Late-stage surprises in the implementation cycle can delay tapeout. Achieve high confidence RTL signoff with the SpyGlass platform by analyzing structural, functional, CDC, timing, power, DFT and physical issues. Signoff RTL for IPs and billion gate SoCs, using a unified hierarchical methodology. Register

SpyGlass Power

A complete RTL to post-layout power optimization and power signoff flow. Proven methodologies that ensure the best possible power reduction while balancing other requirements of the design, such as testability, clock synchronization and ECOs. Verification and estimation are also part of the flow. Register

SpyGlass CDC & Advanced Lint

Signoff CDC verification of a billion gate design using CDC-specific abstraction techniques. Achieve functional CDC verification closure using hybrid CDC verification with formal techniques and functional simulation. Block CDC verification can be closed in hours with automated static signal detection/setup. Formally analyze and verify initialization, finite state machines and dead-code as well. Register

SpyGlass Physical

Quickly identify and fix logical congestion problems during RTL development, avoiding many iterations through physical implementation. Floorplanning early, at RTL, can improve convergence. Analyze and optimize critical timing paths, routing congestion and power; handing off an initial floorplan to the back-end that will ensure predictable closure. Register

GenSys

Address the demanding requirements for RTL restructuring due to physical/power domain re-partitioning, ECOs and architecture changes with an easy to use and automated flow. Automate the assembly of your chip at the architectural level as well. Register

SpyGlass Physical 3D

Unique 3D RTL planning and optimization. Applications include 2.5D silicon interposer and heterogeneous 3D stacked die designs with ultra-fine pitch inter-die connectivity, including CoWos configurations. Also known as Pathfinding, this technology helps you find the right 3D stack configuration in the shortest possible time. Register

SpyGlass DFT, DSM, MBIST

Atrenta’s popular RTL testability solution for advanced technology nodes from 28 to 14nm. Improve stuck-at and at-speed coverage early in the process for both the block and SoC levels. Insert BIST structures automatically at RTL at well. Register

SpyGlass Constraints

Reduce your risk for potential chip failures due to incorrect timing exceptions and missing timing constraints. Enable timing constraints signoff at RTL with SDC validation, management and verification of false/multi-cycle paths using unique formal techniques. Patented constraints management address mult-modes and SoC integration. Register

BugScope

Uncover corner-case bugs, expose functional coverage holes, and increase verification observability by enhancing existing simulation, formal and emulation flows. Automatically generated assertions and functional coverage properties allow progressive and targeted verification of complex designs. Register

Conference Speakers

Atrenta VP of Corporate Marketing Mike Gianfagna and Atrenta Customer Solution Architect Richard Zbranak will join the IP Workshop: Driving Quality to the Desktop of the DAC Engineer

Workshop 6: IP Workshop: Driving Quality to the Desktop of the DAC Engineer
Date and Time: Sunday, June 2, 2013, 1:00 PM - 5:00 PM
Location: 11AB

Atrenta VP of Corporate Marketing Mike Gianfagna Joins John Cooley's Troublemaker Panel
Date and Time: Monday, June 3, 2013, 3:00 PM - 4:00 PM
Location: Ballroom G, Austin Convention Center

Atrenta to present soft IP qualification work daily at TSMC Open Innovation Platform® Theater (booth #1746), Check at TSMC booth for the schedule

 

Atrenta RTL Signoff Theater

Throughout the day, Atrenta will be highlighting customers and partners who are using Atrenta products in a signoff flow. Using an informal interview format, we will explore what these people are doing and what benefits they have achieved. Audience members will be able to ask questions as well. Cadence/Tensilica, CEA-Leti, Cisco, IPextreme, Juniper, Mentor and TSMC are currently scheduled to speak. More speakers may be added, so check the latest schedule at the Atrenta booth during DAC.

 

Designer Tracks

Presentation Session
3.3 - Churning the Most Out of IP-XACT for Superior Design Quality

Speaker: Ayon Dey / Texas Instruments India Pvt. Ltd., Bangalore, India
Authors: Ayon Dey / Texas Instruments India Pvt. Ltd., Bangalore, India
Anshuman Nayak / Atrenta Inc., Noida, India
Samantak Chakrabarti / Atrenta Inc., Noida, India
Samiullah Shaik / Atrenta Inc., Noida, India
Date and Time: Tuesday, June 4, 2013, 10:30 AM - 12:00 PM
Location: 18C

Poster Session
7.46 - Scalable Hierarchical CDC Verification

Speaker: Venkataraman Srinivasagam / Cisco Systems, Inc., San Jose, CA
Authors: Venkataraman Srinivasagam / Cisco Systems, Inc., San Jose, CA
Venkat Ghanta / Cisco Systems, Inc., San Jose, CA
Jaga Shanmugavadivelu / Cisco Systems, Inc., San Jose, CA
Date and Time: Wednesday, June 5, 2013, 12:00 PM - 1:30 PM
Location: Hall 5

Presentation Session
10.5 - Path-Finding Methodology for Interposer and 3D Die Stacking

Speaker: Ravi Varadarajan / Atrenta Inc., San Jose, CA
Authors: Sherry Xiaoxia Wu / Qualcomm Technologies, Inc., San Jose, CA
Ravi Varadarajan / Atrenta Inc., San Jose, CA
Navneet Mohindru / Atrenta Inc., San Jose, CA
Durodami Lisk / Qualcomm, Inc., San Diego, CA
Riko Radojcic / Qualcomm, Inc., San Diego, CA
Date and Time: Wednesday, June 5, 2013, 04:00 PM - 06:00 PM
Location: 18C

 

Celebrate with Us

Kickin up In Austin   Hot Zone DAC Party
Atrenta and Mentor Graphics are proud to sponsor
all the musical entertainment for KICKIN' IT UP IN AUSTIN!

Monday, June 3, 2013, 8:00 PM - 1:00 AM
  Atrenta is also a proud sponsor of the Hot Zone
Monday, June 3, 2013, 8:00 PM - 1:00 AM