Programmed Chip Assembly

GenSys RTL Resources

The need for higher design efficiency in all semiconductor product development has led to an increased focus on IP reuse and platform-based design techniques. The ability to perform comprehensive architectural planning/optimization and communicate the goals of the design to downstream team members with clear specifications and no ambiguity represents substantial competitive differentiation. The goal of these activities is always the same - leverage a design investment across multiple similar socket opportunities, and win those sockets through cost and time-to-market advantages.

The GenSys® Assembly product provides an environment to realize these goals. The product has been in production use for more than seven years on some of the largest designs in the industry, and is very actively used today both at the chip level and on large subsystems and IPs

GenSys Assembly

GenSys Assembly has been developed with leading semiconductor companies servicing the consumer market. The goal of this work has been to reduce front-end development effort for SoC platforms and derivative designs by more than an order of magnitude, while also dramatically reducing the level of human error in assembly. To accomplish these goals, Atrenta has developed a product which fully supports architectural planning and a programmed handoff to back-end design. A well-documented methodology is part of GenSys assembly. Many industry standards, including IP-XACT are supported.

GenSys RTL Snapshot 1

GenSys Assembly Features & Benefits