Atrenta’s GuideWare Reference Methodology

Atrenta’s SpyGlass® platform provides a powerful combination of proven design analysis tools with broad applicability throughout the SoC flow. The SpyGlass platform includes a tool suite for linting, CDC verification, DFT, constraints analysis, routing congestion analysis and power management applicable at RTL as well as the gate level.

SpyGlass enables Early Design Closure® - providing visibility to design risks early and at high design abstractions. During the course of chip development, design goals evolve and get refined from the initial RTL development phase to the final SoC implementation phase. The SpyGlass platform offers a consistent solution that can be used effectively at each stage of the design process to achieve the respective design goals. The use of the right SpyGlass tools at the right stage of design development helps design teams achieve a predictable repeatable methodology.

Atrenta GuideWare is a set of pre-packaged methodologies for SpyGlass. GuideWare reference methodologies have been tested and fine-tuned for high impact results and minimal noise (unnecessary errors). Customers can begin using Atrenta’s GuideWare reference methodologies right away for:

Sample Design Goals Addressed by GuideWare

Customer Adoption of GuideWare is Flexible & Easy

Case Studies for GuideWare Adoption