Atrenta’s GuideWare Reference Methodology
Atrenta’s SpyGlass® platform provides a powerful combination of proven design analysis tools with broad applicability throughout the SoC flow. The SpyGlass platform includes a tool suite for linting, CDC verification, DFT, constraints analysis, routing congestion analysis and power management applicable at RTL as well as the gate level.
SpyGlass enables Early Design Closure® - providing visibility to design risks early and at high design abstractions. During the course of chip development, design goals evolve and get refined from the initial RTL development phase to the final SoC implementation phase. The SpyGlass platform offers a consistent solution that can be used effectively at each stage of the design process to achieve the respective design goals. The use of the right SpyGlass tools at the right stage of design development helps design teams achieve a predictable repeatable methodology.
Atrenta GuideWare is a set of pre-packaged methodologies for SpyGlass. GuideWare reference methodologies have been tested and fine-tuned for high impact results and minimal noise (unnecessary errors). Customers can begin using Atrenta’s GuideWare reference methodologies right away for:
- Quick out-the-box benefits - achieve broad-based design goals and from the RTL phase to the final SoC implementation phase
- Quick deployment - of the SpyGlass solution to global design teams
Sample Design Goals Addressed by GuideWare
- Will the design simulate correctly?
- Are clocks and resets defined correctly?
- Will the design synthesize correctly? Are there unintended latches or combo loops?
- Will gate simulations match RTL simulations?
- What will the test coverage be?
- What is the power consumption of a given block?
- What is the profile of this IP? (For example, gates, flops, latches, RAMS/ROMS, I/Os, tristates, clocks)
- Are there any inherent risks or non-standard design practices used in this IP?
- Are there any adaptation issues in the target SoC, such as power, routability or congestion?
- Are all the incoming blocks truly ready for integration? Are they clean in terms of clocks/resets and constraints?
- What are possible inter-block issues? (For example, are block-level constraints complete and coherent with target SoC constraints?)
- What are "common-plane" issues among heterogeneous blocks? (For example, scan chain management and test blockages at the SoC level)
- Can I leverage my block-level work (waivers, constraints) at the SoC level?
Customer Adoption of GuideWare is Flexible & Easy
- Customers with existing SpyGlass templates (rule-sets) can leverage the work done by Atrenta SpyGlass experts in terms of which rules to use, when to use them and how best to use the rules. A simple comparison of customer templates with GuideWare templates provides a quick start for enhancing the design flow
- Customers starting out with SpyGlass deployment can get started with GuideWare templates immediately and enhance them over time
Case Studies for GuideWare Adoption
- A large IDM ran GuideWare templates on their IP blocks, found critical errors in one IP block, compared GuideWare templates to their existing templates, and enhanced their existing templates for better problem coverage. The whole effort took less than one week
- A large consumer electronics company adopted GuideWare as-is for their next generation methodology improvement. The whole effort of detailed methodology review, results validation and deployment feasibility took less than 2 weeks