Requirements for Soft IP Qualification, The IP Kit
This white paper focuses on how SoC designers and integrators can effectively assess the quality and completeness of soft IP cores. A methodology for accomplishing this goal is presented, and an overview is provided of the Atrenta IP Kit - an application of the SpyGlass® platform that implements a soft IP quality qualification methodology.
Avoiding Pitfalls While Specifying Timing Exceptions, SpyGlass TXV
In this white paper we will discuss various types of exceptions and describe how to avoid pitfalls using a systematic verification approach. Implementation tools such as synthesis and place and route make use of this information to better optimize the implementation and achieve better area, timing, power or routability. While timing exceptions are potent tool in the hands of implementation engineers, any mistake in specifying them can result in a chip failure.
How to Achieve Power Estimation, Reduction and Verification in Low Power Design, SpyGlass Power
Power dissipation is a major concern in modern day IC design. For wireless electronic appliances, battery life is one of the major influencers of the purchase decision and can be an effective differentiator. Mobile phones, PDAs, digital cameras and personal MP3 players are increasingly being sold on the long battery lives.
This White Paper discusses a solution for clock gating analysis and implementation at RTL for power reduction. The RTL approach is important because designers usually verify power only at the gate level and any change to the RTL needs many design iterations to reduce power. The RTL solution thus saves weeks of effort by fixing potential power issues up-front.
Congestion Mitigation During RTL Development, SpyGlass Physical
Early physical design closure is critical for successful SoC delivery. Routing congestion is one of the key aspects of physical design closure. In this paper we have focused on the logical congestion aspects. We have established the need for a solution geared towards RTL authoring and creation teams. Some products are beginning to emerge in the EDA marketplace to tackle the congestion problem described above. SpyGlassÂ® Physical, a new product in the Atrenta SpyGlass family, is aimed specifically toward RTL designers and offers many capabilities to resolve logical congestion issues up front, during RTL development. The product has very easy to use physical rules with debug capabilities to pin point the root cause, as well as simple reports with the congestion status of RTL blocks.
SoC Physical Closure Begins at RTL!, SpyGlass Physical
Any survey of chip design teams consistently points to two problem areas impacting quality and schedule of today SoCs. Those areas are: a) completeness of verification, and b) physical design closure for area, timing and power for complex IPs and SoCs. With the advent of deep sub-micron technology, these problem areas have become exacerbated. In this White Paper, we take a closer look at the physical design closure aspects of advanced SoCs. We provide a root cause analysis of unpredictable physical design closure issues and explore possible solutions and methodologies to address these problems.
An Automated Approach to RTL Memory BIST Insertion and Verification, SpyGlass DFT MBIST
This white paper describes a novel approach for memory built-in self test (MBIST) and repair insertion at the register transfer level (RTL). The approach is independent of BIST IP technology and works with any supplier\'s qualified ASIC design kit and BIST libraries. The methodology describes both a bottom up and a top down approach to SoC design and validation - all at the RTL stage. Application of this approach on real industrial designs indicates enhancement of design productivity and shorter cycle time for functional validation.
This paper describes a method for estimating fault coverage from register transfer level (RTL) descriptions of complex circuits. The method does not require automatic test pattern generation (ATPG) or the use of fault simulation and therefore offers the advantage of very rapid turnaround with no additional user effort. An important benefit is the means for a user to quickly determine the change in fault coverage while considering various changes to a design. The technique automatically takes advantage of available designed in test logic and may be applied to either combinational or sequential test generation tools.
This white paper demonstrates a solution for facilitating at-speed test at the register-transfer level. The RTL approach is important, because designers and test engineers usually verify the test coverage only at the gate level during the final ATPG stage. This RTL solution thus saves weeks of effort by fixing potential issues up front.
Design for test (DFT) techniques impose rigorous and generally well-known constraints on a design. These constraints include issues with respect to clock generation and distribution, asynchronous sets and resets, memory controls and tristate busses.
Analysis of Random Resistive Faults and ATPG Effectiveness at RTL, SpyGlass DFT
Traditional netlist-based DFT analysis runs into design rule violations during scan insertion in synthesis and needs RTL designers to modify the design for uncontrollable clocks and resets. Similarly, low fault coverage during ATPG results in designers having to modify RTL to improve observability and controllability causing many design iterations and schedule impact.
Constraints Management: Approach and Techniques for Preserving the Intent of Timing Constraints throughout the Design Flow, SpyGlass Constraints
Constraints management is a major concern for designers today and increasing design complexity, coupled with mounting time to market pressure, makes faster timing closure and reduced iterations a necessity. Any late stage constraint change brings with it enormous costs, both in terms of time and money, and can lead to a failed design project.
Do your Chip a Favor! Manage the Constraints!!, SpyGlass Constraints
Design goes through several transformations in a typical RTL-to-layout flow. There are several verification steps in place to make sure that the design intent has not changed. For example, simulation, equivalence checking and so on. In practice, Timing Constraints are created at RTL level just as RTL is created and are refined throughout the design cycle
Combining Structural and Functional Verification Techniques to Improve Effective CDC Verification, SpyGlass CDC
Multiple, independent clocks have become a fact of life on SoCs and other complex ASICs. In extreme cases, such as in large communications processors, clock domains may number in the thousands. Clock domain crossings pose a growing challenge to chip designers
Verification of Multi-Clock Designs - The Bigger Picture, SpyGlass CDC
This white paper outlines a holistic approach to resolving issues associated with ever increasing numbers of clock interfaces, where data is transferred between clocks of different frequencies and often between asynchronous domains. The paper suggests exercising various technologies as part of an intuitive user environment, and highlights why addressing one issue in isolation can at best jeopardize timing closure, and at worst introduce silicon risk.
Understanding Formal Verification Concepts - Part 1, SpyGlass CDC
This paper describes formal verification concepts and the differences between formal and simulation techniques, especially in the context of assertion-based verification. The assertion- based verification flow and some of the formal verification algorithms are also discussed in detail. Last but not the least, a few applications of formal technology in the context of ASIC designs are also listed.
Understanding Formal Verification Concepts - Part 2, SpyGlass CDC
In this second white paper in a three-part series about formal verification concepts, we examine the assertion-based verification flow and some of the formal verification algorithms. This kind of approach has become necessary as SoC designs become more challenging and as the traditional method of simulation proves too slow, too costly, and insufficient in terms of coverage.
SpyGlass Lint and CDC are critical analysis tools for RTL designs that identify chip killer problems and shorten design cycle time. This document highlights the issues that come up when taking a XILINX FPGA-based design through the default SpyGlass flow. With a script-ware based approach, the work required to make the design SpyGlass compatible is significantly reduced. The approach takes care of handling Xilinx library files, design files and design constraints.
CDC Verification of Billion Gate SoCs, SpyGlass CDC
Driven by growing design sizes and complexities and aggressive power requirements, design and verification engineers are witnessing an explosion in the number of asynchronous clocks. Consequently, design and verification teams spend a huge amount of time verifying the correctness of asynchronous boundaries on the chip. The paper describes three methodologies to address this issue and the benefits of each.
SpyGlass Application in an FPGA to ASIC Conversion, SpyGlass
Mapping an FPGA design to an ASIC can be a problem-free experience if the FPGA was designed from the outset with a re-map in mind. If you did not take this precaution, you may find that so many changes are required to make the FPGA RTL ASIC-compliant that you must effectively re-design and re-verify the RTL. In this case, the FPGA implementation becomes little more than an existence proof that a working implementation can be built. By following the Atrenta GuideWare™ methodology using the SpyGlass® family of tools, you can achieve portability of the design from the FPGA implementation to the ASIC implementation, and from one process node to the next. Atrenta\'s GuideWare methodologies contain a comprehensive set of checks and qualified templates that allow for maximal portability of the design.
Lint Your Hardware Description: The Need to be Fast, Accurate, Scalable and Flexible, SpyGlass
A reliable linting tool must be SAFE (Scalable, Accurate, Fast and Extendible) so it can help catch issues early in the design cycle â€“ issues that may be missed by traditional dynamic verification techniques. The main objective of a SAFE linting solution is to reduce costly design iterations, prevent late stage design ECOs and promote seamless reuse of IPs. Such a linting solution will need to co-exist with dynamic verification tools to complete the verification eco-system.
Techniques for FSM Design and Verification, SpyGlass
Large system-on-chip (SoC) designs contain many finite state machines (FSMs), which combine with data paths, memories, and other components. FSMs are sources of functional bugs in SoCs. Designers often attribute poor timing, power, and performance to poor FSM design. Although verification tools can perform checks on FSMs, such as deadlock and unreachable states, these tools may not consider all aspects of FSM design styles.
In this White Paper we will discuss FSM functional issues, metrics, design styles, and systematic validation approaches.
This White Paper deals with the way SoCs are designed, a process of substantial complexity. This design process is undergoing significant transformation, and those changes are a central part of this piece.
Advances in silicon technology have enabled unprecedented levels of integration in today\'s SoC designs. This white paper describes typical issues faced by designers in a typical work-flow for today\'s SoC designs that includes new block/subsystem RTL development, IP selection and SoC level integration. The paper highlights the need to address implementation issues for the chip project early in the design cycle. The paper then reviews current \"rule-checking\" approaches and gives an overview of the Atrenta approach to the problem.
We all know that hierarchy created for logic design must often be adjusted to map to a physical implementation. Logic hierarchy is typically constrained by non-implementation factors, especially organization of teams working on different components and use of legacy or 3rd party IP. Physical hierarchy, on the other hand, must partition the logic to fit detailed implementation tool capacity limits and to optimize for timing and area. These competing needs are unlikely to align by chance and forcing alignment at design start is not an option open to most. For the implementation cycle, this problem is solved. All physical design tools provide methods to restructure logic. So, what’s the issue? As always, technology and needs have advanced in ways that require at least part of this solution to be re-thought from the ground up. Deep sub-micron design is driving a need for multiple physical trials during the evolution of the RTL. This forces implementation teams to restructure multiple times with scripts that must be re-designed for every re-map, slowing down the process and limiting the number of possible trials.
Physical-aware RTL Restructuring for SoC Cost Reduction, GenSys RTL
RTL restructuring has become an essential step in many design flows. This white paper discusses how the combination of the SpyGlass Physical and the GenSys RTL solutions reduces the effort required to implement physical-aware RTL restructuring by orders of magnitude, turning what has been a painful task into a simple automated process to optimize designs.
Automated Assembly and IP Integration Techniques for SoCs, GenSys Assembly
Platform-based methodology is projected to become the dominant approach for SoC design in the very near future. Automated assembly techniques equally will become the standard approach for building these designs in order to manage complexity, time to market and development cost. Adopting such techniques can have significant impact on each of these factors and carries a significantly lower startup cost than many people assume. More importantly, these techniques are starting to become a competitive advantage, especially in consumer segments. In this White Paper, we have reviewed the key steps needed to implement automated assembly methods. We have reviewed the costs and benefits associated with these tasks and discussed how they are working today for real designs.
As the popularity of reusing existing designs or intellectual property (IP) blocks continues to grow, design challenges escalate. As time to market pressures and product complexities increase, the pressure to reuse complex building blocks increases significantly. The solution to the productivity problem is increasing the abstraction level in design technology and introducing tools to support re-use of components and system parts. Apart from existing methodologies, one new approach is to create derivative designs on top of existing ones, which is called derivative design methodology. This paper covers each step of a derivative design flow one-by-one.
Automated Assertion Based Verification Methodologies for IP and SoC Development, BugScope
SoC designs today are composed of many highly complex IPs, each of which may be developed by different teams. The complexity of the SoC, and even the individual IP has now grown to the point that verification itself is typically managed by a separate, dedicated team. This division in labor necessitates the need for automation verification that is embedded within each IP. Automated assertion synthesis is the only practical, proven technology available today that enables a targeted verification methodology spanning the entire design flow, from early IP-level development to SoC integration and System-level HW / SW co-verification.