Atrenta SpyGlass® in the Xilinx Vivado™ Design Suite
FPGA designs are becoming highly complex – as complex as ASIC designs, Recognizing these challenges, Xilinx has introduced the Vivado™ Design Suite, a revolutionary IP and system-centric design environment built from the ground up to accelerate the design of not only programmable logic and I/O but ‘All Programmable’ devices.
SpyGlass is part of the Vivado Design Suite and checks the pre-synthesis RTL for connectivity, synthesis/simulation readiness, and structural completeness. Asynchronous clock crossings and timing constraints are also checked to ensure correctness.
The benefits of a SpyGlass Clean design are now extended to Xilinx programmable device design.
The Vivado Design Suite is available from Xilinx. SpyGlass additions to the flow are available from Atrenta.