GenSys® Assembly

Programmed Chip Assembly

The need for higher design efficiency in all semiconductor product development has led to an increased focus on IP reuse and platform-based design techniques. The ability to perform comprehensive architectural planning/optimization and communicate the goals of the design to downstream team members with clear specifications and no ambiguity represents substantial competitive differentiation. The goal of these activities is always the same – leverage a design investment across multiple similar socket opportunities, and win those sockets through cost and time-to-market advantages.

The GenSys® Assembly product provides an environment to realize these goals. The product has been in production use for more than seven years on some of the largest designs in the industry, and is very actively used today both at the chip level and on large subsystems and IPs

GenSys Assembly

GenSys Assembly has been developed with leading semiconductor companies servicing the consumer market. The goal of this work has been to reduce front-end development effort for SoC platforms and derivative designs by more than an order of magnitude, while also dramatically reducing the level of human error in assembly. To accomplish these goals, Atrenta has developed a product which fully supports architectural planning and a programmed handoff to back-end design. A well-documented methodology is part of GenSys assembly. Many industry standards, including IP-XACT are supported.

GenSys RTL Snapshot 1

GenSys Assembly Features & Benefits

  • Fully interoperable (import and export) with several standards including IP-XACT, Verilog and VHDL (both designs and components), CSV and Tcl
  • Support for a bottom-up design methodology through standard hierarchical methods and a top-down design methodology through the ability to change hierarchy on the fly, and create/edit new components in place
  • Support for a spreadsheet-based paradigm, familiar to most designers, with batch and graphical use-models which are fully interchangeable
  • Support for template-based report generation, providing a simple way to generate custom reports
  • Comprehensive connectivity checking with sort/filter options to review how and why connections are made, and a direct connection to the SpyGlass® suite for a broad range of design analysis
  • Interface-based connectivity reduces user-defined connections by 95% or more. Ad-hoc connectivity is also supported through a high-productivity interface
  • Support of a comprehensive set of connection techniques with splices and overrides to handle permanent and temporary tie-offs and opens handling all the special cases that happen in real designs
  • User-definable auto-connect techniques aid completion of many connections
  • Builds "correct-by-construction" chip and sub-system assemblies, reducing time to capture and debug
  • Shows immediate benefits in turnaround-time for capture and edit of full-chip designs
  • Helps dispersed design teams to create more consistent, high-quality designs
  • Exploits the full power of effective design re-use and IP integration
  • Integrates seamlessly into existing design environments, dramatically enhancing efficiency of installed tools and methodologies
  • Silicon proven on multiple designs
  • Over 20x reduction in chip/sub-system assembly effort over traditional methods as verified by a major IDM