Architecture Generation & Programmed Handoff

The need for higher design efficiencies in all semiconductor product development has led to an increased focus on IP reuse and platform-based design techniques. The ability to perform comprehensive architectural planning/optimization and communicate the goals of the design to downstream team members with clear specifications and no ambiguity represent substantial competitive differentiation. The goal of these activities is always the same – leverage a design investment across multiple similar socket opportunities, and win those sockets through cost and time-to-market advantages. The 1Team®-Genesis product provides an environment to realize these goals.

The 1Team-Genesis solution has been developed over more than three years with a leading semiconductor company servicing consumer markets. The goal of this work has been to reduce front-end development effort for SoC platforms and derivative designs by more than an order of magnitude, while also dramatically reducing the level of human error in assembly. To accomplish these goals, Atrenta has developed a product that moves beyond early market concepts of platform-based design as the starting point for a new chip RTL, to a system which fully supports architectural planning and a programmed handoff to back-end design.

• Interface-based connectivity reduces user-defined connections by 95% or more. Ad-hoc connectivity is also supported through a high-productivity interface
• Support for a bottom-up design methodology through standard hierarchical methods, and a top-down design methodology through the ability to change hierarchy on the fly, and create/edit new components in place
• Support of a comprehensive set of connection techniques with splices and overrides to handle permanent and temporary tie-offs and opens – handling all the special cases that happen in real designs
• User-definable auto-connect techniques aid completion of many connections
• Comprehensive connectivity checking with sort/filter options to review how and why connections are made, and a direct connection to the SpyGlass® suite for a broad range of design analysis
• Traceability of who created an object or made a change and when
• Support for a spreadsheet-based paradigm, familiar to most designers with batch and graphical use-models, which are fully interchangeable
• Fully interoperable (import and export) with several standards including IP-XACT, Verilog and VHDL (both designs and components), CSV and Tcl
• Support for register management and automated netlist generation
• Support for template-based report generation, providing a simple way to generate custom reports
• Silicon proven on multiple designs

• Builds "correct-by-construction" chip and sub-system assemblies, reducing time to capture and debug
• Works smoothly even with a traditional RTL methodology
• Shows immediate benefits in turnaround-time for capture and edit of full-chip designs
• Reduces or eliminates the need for re-spins, potentially saving millions of dollars
• Enables early closure of hand-off ready chip netlists
• Helps dispersed design teams to create more consistent, high-quality designs
• Exploits the full power of effective design re-use and IP integration
• Integrates seamlessly into existing design environments, dramatically enhancing efficiency of installed tools and methodologies
• Over 20x reduction in chip/sub-system assembly effort over traditional methods as verified by a major IDM