Specify Constraints Early, Validate Continuously & Automate Handoff
Creating and ensuring correct and consistent constraints, at all levels of the design hierarchy and throughout the design
cycle, is a vital and increasingly challenging task. The difficulties can include: writing new constraints; managing thousands of lines of
legacy constraints; managing thousands of timing exceptions across the design flow; unwanted iterations due to changing constraints;
and erroneous constraints resulting in redesigns and even re-spins.
The SpyGlass® Constraints solution provides a big productivity boost to IC design efforts by automating the
creation, validation and management of constraints. The SpyGlass Constraints solution generates new constraints where needed and verifies
that existing constraints are correct and consistent across all phases of development: pre-synthesis, pre-layout and post-layout.
Faster, Better IC Design The SpyGlass Constraints solution can trim weeks
or more from design schedules by pin-pointing the root cause of constraint problems quickly. By ensuring valid constraints,
the SpyGlass Constraints solution can avert design flaws and costly re-spins. The solution also helps assure a smoother hand-off between
tools in multi-vendor flows. In addition, advanced options greatly streamline one of the most complex of constraints management tasks
by automating timing exception generation and verification.
Generate, Validate Constraints--Automatically
The SpyGlass Constraints solution automatically generates new constraints from RTL or netlists, based on the topology
of the design. It identifies clocks--including generated clocks--and associates all inputs with the correct clocks. The SpyGlass Constraints solution
understands multiplexed inputs, identifies clock domain crossings and generates false path constraints at those crossings.
The SpyGlass Constraints solution checks new constraints and legacy constraints against RTL and netlists to verify
correctness and completeness at each stage. The SpyGlass Constraints solution also checks for consistency among constraints--e.g.,
between multiple block-level constraints and between block- and top-level constraints. The SpyGlass Constraints solution also understands
complex case analysis in order to make sure that all modes are addressed, within and across constraints files for different modes and corners.
Timing Exception Generation and Verification
The SpyGlass Constraints solution offers features that greatly simplify the difficult task of timing exception management.
The Timing Exception Verification (TXV) feature automatically verifies the correctness of exceptions that designers have previously specified.
TXV uses sophisticated techniques to examine the netlist to identify timing–critical false and multi-cycle paths.
The Methodology
The SpyGlass Constraints solution methodology provides a structured, easy to use and comprehensive
method for solving constraint problems that ensures quality results with fewer but meaningful violations, thus saving time.
- Provides methodology documentation and rule-sets as part of the product
- Outlines a methodology to optimize constraints at block level and chip level, at RTL, pre-layout and post-layout stages. The steps include design setup, creating of new SDC constraints, cleaning clock and delay constraints, fixing timing exceptions, resolving hierarchical constraint mismatches, and creating timing-critical timing exceptions post-static timing analysis
Features & Benefits
- Automatically creates and verifies constraints
- Ensures that constraints are correct and consistent throughout the design flow, from RTL through floorplanning
- Validates consistency and correctness at all levels: chip-to-block and block-to-block
- Can save weeks or months of manual creation and verification effort
- Simplifies management of legacy constraints
- Prevents design errors and respins
- Results in better-optimized silicon
- Supports RTL and netlist input
- Supports full Tcl-based SDC, compliant with Design Compiler, PrimeTime and BlastFusion constraints formats
- Flags redundant and over-specified constraints
- Advanced options automate timing exception generation and verification
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