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Design for Low Power at RTL
With the SpyGlass® Power solution policies, users can tune their designs for power consumption and efficiency at the register transfer level (RTL). The SpyGlass Power solution provides early information about power consumption at RTL, and provides guidance where power can be reduced. The SpyGlass Power solution not only detects, but can also automatically fix, key power management issues.
The advantages are significant. Traditional approaches address power analysis and optimization at the gate level, making changes difficult and costly and complicating verification. The SpyGlass Power solution, by contrast, enables users to tune power characteristics during RTL creation, when the design impact is greatest and the cost of modifications lowest. It can significantly shorten development cycles, reduce costs and improve the power characteristics of the finished product.
Low Power Methodology Guidance
Using circuit activity data from simulation, the SpyGlass Power solution minimizes dynamic power by ensuring the most effective RTL clock gating strategy. It also includes a complete set of power reduction techniques addressing data path controls, clocks, buses and memory units.
The SpyGlass Power solution also helps users manage the complexity of multiple power and voltage domains: they can verify, visualize and analyze multiple domains and domain crossing issues.
The SpyGlass Power solution includes an intuitive design and diagnostic environment combining RTL design capture and browsing with schematic visualization. Users can easily cross-probe between violation reports, schematics and RTL windows to trace problems to their source and make appropriate changes.
The Methodology
The SpyGlass Power solution methodology provides a structured, easy to use and a comprehensive method for solving power design issues, thereby ensuring high quality RTL.
- Provides methodology documentation and rule-sets are part of the product
- Walks users through a series of recommended steps to estimate power, reduce power, and ensure the design complies with the "power intent" defined in UPF or CPF formats
Features & Benefits
- Estimates power at RTL and gate-level
- Reduces power -- dynamic analysis for clock gate insertion
- Guides optimal power design at RTL
- Analyzes power issues at block and chip level--at RTL or gate-level netlist
- Verifies, visualizes and analyzes voltage and power domain management
- Verifies that voltage level shifters and isolation logic are correct
- Intuitive, integrated debug environment with cross-probing among views
- Supports UPF and CPF power formats
The SpyGlass Power solution encompasses power estimation, reduction and verification capabilities. |
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